1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to vertical channel flash memory devices.
2. Description of Related Art
1. To maintain enough current through the channel, the memory cell takes more area with traditional ETOX (EPROM with Tunnel Oxide) structure since the channel is parallel to the wafer surface.
2. During the programming and the erasing procedures, the tunneling electron always needs to traverse (pass through) part of the channel area resulting in charge trapping and transconductance degradation.
In accordance of this invention, a vertical memory device on a silicon semiconductor substrate is provided including the following features. An array of isolation silicon oxide structures are formed on the surface of the silicon semiconductor substrate. There is a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. The sidewalls of the floating gate trench are doped with a threshold implant through the trench sidewall surfaces. There is a tunnel oxide layer on the trench sidewall surfaces. The tunnel oxide layer has an outer surface. There is a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Source/drain regions are formed in the substrate self-aligned with the floating gate electrode. An interelectrode dielectric layer overlies the top surface of the floating gate electrode. A control gate electrode overlies the interelectrode dielectric layer above the top surface of the floating gate electrode. There is an ion implanted source line formed in the substrate after a self-aligned etch.
Preferably, the trench has a depth from about 2,000 xc3x85 to about 8,000 xc3x85. The tunnel oxide layer has a thickness from about 70 xc3x85 to about 150 xc3x85. The floating gate electrode comprises doped polysilicon having a thickness of from about 1,000 xc3x85 to about 4,000 xc3x85. The threshold implant comprises ion implantation of boron fluoride ions which were ion implanted at an energy from about 20 keV to about 50 keV with a dose from about 1 E 12 ions/cm2 to about 5 E 13 ions/cm2. The source/drain implant comprises arsenic which was ion implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 15 ions/cm2 to about 5.5 E 15 ions/cm2 with a dopant concentration after annealing from about 1 E 20 atoms/cm3 to about 5 E 21 atoms/cm3. A source line was formed after a self-aligned etch to a depth from about 1,000 xc3x85 to about 3,000 xc3x85 on the source side of the trench. The source line was formed by an implant provided by ion implantation of dopant selected from the group consisting of arsenic and phosphorus ions implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 14 ions/cm2 to about 5 E 14 ions/cm2.
Features of this Invention
1. A cell structure in accordance with this invention uses a vertical channel rather than a traditional horizontal one.
2. Since the channel has a vertical orientation with respect to the wafer surface, the activity area of the cell in accordance with this invention can be larger while requiring less silicon surface area compared to a conventional cell with an ETOX structure. Therefore, the unit cell will requires less silicon surface area compared to a conventional one.
3. Only a single mask is required to conduct stacking gate etching of a memory cell and control gate etching of peripheral devices simultaneously instead of two masks employed separately for a conventional ETOX structure.
4. During the erasing procedure, the band-to-band hot hole phenomenon can be completely prevented with a memory cell, in accordance with this invention.